Integrated circuit (IC) technology is often used to implement logic functions. Some ICs provide combinationatorial and sequential logic functions that are user-programmable. One class of such ICs uses programmable logic gates to implement desired functions and to drive the output. Another class of these ICs employs memory units, each of which utilizes the input signals as its memory address and outputs its stored content as the desired functional combination of the address bits. These devices are generally known as programmable logic devices (PLDs). Different methods of implementing PLDs abound in the literature of this field.
One type of PLD is known as a field programmable gate array (FPGA), which usually contains an array of modularized logic function generators and programmable interconnects. It is an array of uncommitted gates with uncommitted wiring channels. Each logic cell can be programmed to implement a particular logic function. A gate array circuit can be programmed to implement virtually any set of functions. FPGAs generally use look-up tables (LUTs) or universal logic modules (ULMs).
A look-up table is an addressable array or a matrix of memory units that contains data and can be searched by addressing and accessing individual memory units. Therefore, by programming predetermined values into the memory array, the LUT can implement any function of the input variables. FPGAs can be manufactured to allow a combination of LUTs to be grouped together to implement larger functions.
FIG. 1 shows a 2-input LUT according to the prior art. This LUT is disclosed in U.S. Pat. Nos. 4,642,487 and 4,870,302. The circuit contains four SRAM memory cells (M1 to M4), six NMOS pass gates n1-n6, and three inverters inv1-inv3. This implementation requires 24 NMOS and 6 PMOS devices. The NMOS pass gates cause a Vt drop, and thus, there is a need for a recovery circuit.
As process technology scales down to 0.13 micron, 90 nm, and beyond, the Vdd voltage is also scaled down to below 1.2V. Furthermore, the pass devices n1-n6 ineffectively pass Vdd due to the Vt drop of the NMOS. Thus, transmission gate devices are substituted by the ones shown in FIG. 2 (see also U.S. Pat. Nos. 5,719,507 and 6,809,552). However, this implementation also requires 24 NMOS and 16 PMOS devices, not including the buffer inverter inv3.
The prior art look-up tables, as illustrated above, use a relatively large number of devices, which result in LUTs that consume valuable silicon area. In addition, there is a high amount of power leakage, which may well become a serious limitation for FPGAs that are used in battery-operated applications.